In addition to mainstream codecs like MP3, AAC, WMA, RealAudio, etc. it is also necessary to support compute-intensive lossy and lossless HD audio codecs such as those from Dolby and DTS. Bit rates supported by some HD audio standards can be as high as 24.5Mbps, as opposed to less than 1Mbps for previous-generation codecs. These market requirements translate into demand for efficient audio platforms that utilise smaller die size and consume lower power without compromising on audio performance and quality.

 

The CEVA-TeakLite-III family of DSP cores allows IC companies to design an audio subsystem for their multimedia ICs, using a powerful single core, small local memories, and high-latency DDR support for efficient codec implementations.

Significant differences exist between standard and HD audio specifications, in terms of processing complexity, number of audio channels, bit rates and precision requirements. These new demands from HD audio systems impact every aspect of Integrated Circuit (IC) design and create major challenges to delivering the audio quality promised by such new home entertainment devices. For example, internet enabled DTV and STB devices and streaming TV services, require support for multiple audio codecs, with a larger presence of HD audio standards, using highly compute intensive lossy and lossless codecs.

Furthermore, in addition to HD audio codecs, DTV manufacturers are differentiating their products via specialised audio post-processing algorithms, a need which stems from the small, thin, low powered and badly positioned DTV speakers, coupled with user' s expectation for improved audio experience. This means that the DTV audio processor must be powerful enough to handle not just HD audio codecs, but also multiple post-processing effects such as virtual surround (stereo to 5.1 widening), automatic volume, virtual bass and dynamic range compression.

To complicate things further, a modern STB needs to simultaneously decode three or more audio streams. For example, view one stream on a DTV, record a second to a DVR (may involve encoding to save disk space), and transcode a third to a mobile device to take with you out of home (may involve decode + encode to a different format to suit the mobile device). Such simultaneous audio decoding and encoding overloads the audio processor and requires it to be of very high performance. A different, but similarly demanding scenario is associated with multi-device support, as occur with the new class of home media gateways which require distributing audio to various devices in the home, such as DTV, PC, Internet tablet, Smartphone and more. These home media gateways are clearly required to support transcoding (decoding of one format, and encoding to another) of multiple audio streams to different devices, and distribute them using schemes such as DLNA.

Home audio IC design challenges

Deducing from these home audio use-cases, when designing a multimedia IC for home entertainment, the audio processor or subsystem of such IC must deal with challenges that are no less stringent than those of video or graphics, and would include:

Lossy and lossless HD audio codecs processing – meeting the quality criteria of lossy codecs such as Dolby Digital Plus and DTS-HD High Resolution, and the bit exact criteria of lossless codecs such as Dolby TrueHD and DTS-HD Master Audio. Additionally, quality metrics of these audio standards makes it required to use a wide dynamic range, typically much wider than the inherent 24-bit audio samples data width. These codecs are computation intensive, and poses a challenge of computation ability and wide dynamic range.

Very high bit-rate codecs – an HD audio standard such as DTS-HD Master Audio uses a maximum bit-rate of 24.5Mbps, resulting in a massive amount of data, and consequently, a large and costly on-chip data RAM.

Multi tasking use-cases – the need to process multiple streams (each consists of multiple audio channels), and audio post processing effects, such as in a DTV or STB, makes it required to task-switch or swap between tasks, which poses an overhead of code and data swap. Swap interval would have significant effect on the audio subsystem design, for example, swap every frame as opposed to a swap every 10 frames, would affect the required processor MHz, the required L1 code and data memory size, and external memory bandwidth.

System constraints - as the IC' s audio and video subsystems would have different external DDR access time and bandwidth (video typically having higher priority), the audio subsystem must be robust enough to cope with high DDR latency, typically in the range of 100-500 processor cycles.

Software wise, the challenge of implementing and certifying HD audio codecs from Dolby and DTS for a new audio processor, is very resource consuming, and can require many man-years of effort.

Finally, the usual cost pressure and price erosion of ICs, makes it necessary to minimise the number of on-chip processor cores, use small L1 memories and slower (cheaper) external DDR memory. Cost is also driving these non-portable devices to be lower power, not just for environmental reasons, but also in order to allow for lower heat dissipation and the use of cheaper IC packaging.

Solution approaches

By its nature, audio signal processing calls for a Digital Signal Processor (DSP), and the recent trends observed here have made it required to use a much more powerful DSP. This is clearly evident when looking at several multimedia ICs, such as STMicro’s FLI7510 DTV IC that uses two audio DSPs, clocked at 450MHz each, while Sigma Design’ s latest SMP8910 IC uses three audio DSPs, running at 400MHz each. Both of these ICs use a home-grown DSP (by the respective vendors), and are using multiple instances of these audio DSPs due to the massive amount of audio processing carried out.

 

An alternative single-core solution is offered by CEVA in the form of the CEVA-TeakLite-III family, which consists of the CEVA-TL3210 core and the new CEVA-TL3211 DSP core. This is a family of cores having a native data width of 32-bit and an arithmetic accumulation (or dynamic range) of 72-bit, to address most demanding HD audio use-cases.

The CEVA-TL3211 is a next-generation audio DSP core, running at 1 GHz with a silicon footprint of only 0.2mm² at a 40nm process. This single core licensable audio processor solution addresses current and future HD audio requirements for extreme processing, increased flexibility of design and use, ultra-low power consumption, and ease of programming.

It consists of a high-performance, low-power, fully synthesizable CEVA-TeakLite-III DSP engine coupled with a configurable L1 program and data cache memories and TCMs, support for high-speed AXI system busses, an integrated Power Scaling Unit (PSU), and a full suite of certified and optimised Dolby and DTS HD audio codecs, which when combined is able address every aspect of the HD audio IC design challenges faced by design engineers.

 Author: Moshe Sheier is director of product marketing at CEVA