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According to Moore's Law, the number of transistors that can be placed on an integrated circuit (IC) increases exponentially, doubling approximately every two years. While the semiconductor industry has taken full advantage of this scaling, steadily increasing the number of components per chip, more components translate into greater design complexity and an increase in the amount of time required to complete a design. One area where this added complexity proves especially problematic is layout. Problems arise not only because more components must be laid out, but because the circuit and layout designers are often two different people, making communication of device attributes difficult.
Automation technologies like schematic-driven layout (SDL) offer one way of addressing this complexity, while also improving productivity.Yet, automation without control often forces designers to face undesirable tradeoffs between setup time and layout speed. With next-generation custom chips promising to be bigger and even more complex, the time for another leap forward in productivity has come. That leap - controllable automation enabled by flexible device generation technology - promises to take SDL far beyond mere drag-and-drop device generation. Not only does it place more control of the automation in the hands of the designer, but it also enables a range of capabilities to aid designers in realising superior layout results in less time and with less effort.
Road to automation
To better understand where the industry is headed with automation, it is necessary to first look back at where it has been. In the early years of semiconductor development, IC designs were tediously hand drawn on mylar graph paper and manually transferred to photomasks. As computer performance improved, hand-drawn circuits were captured in crude Computer-Aided Design (CAD) systems. Polygon layout editors came next and enabled designers to work directly on the computer. Schematic editors followed, allowing designers to draw circuit designs graphically on workstations. But communicating design intent from the circuit designer to the layout designer remained difficult, and required laborious review of the schematic and detailed, manual transfer of device attributes to layout. Layout vs. Schematic (LVS) and Design Rule Check (DRC) computer programs were introduced to catch connectivity/wiring errors (LVS) and manufacturing rule violations (DRC).
A big leap in productivity was realised with the introduction of SDL, a technology that allows designers to automatically create a physical layout from a logic schematic. In a SDL flow, users simply select components in the schematic and "drag" them into the layout editor which then automatically creates the physical design.
Today, analogue and custom digital IC designers create schematics using symbols that correspond to specific devices. They assign values for a variety of parameters prior to layout based on the results of simulations run using foundry provided models. In the case of custom layout design, flexible configurations are required to create a design with optimal performance and the densest possible layout. Consequently, designers typically require a large variety of device sizes, meaning that hundreds or even thousands of different device versions would be required to create a useful and automated SDL flow. The introduction of the parameterized cell (PCell) brought an answer to this dilemma.
PCells are software "scripts" or sequences of commands used to define physical layout based on a prescribed set of parameters. A single PCell takes the place of many fixed cells by allowing the substitution of different values for specified dimensional variables or parameters. The scripts, written primarily in proprietary formats but also using an industry-standard format like Tcl, describe what the layout tool should do when an instance of the cell is used in the design. The parameters quantify the dimensions for the variables specified in a given instance.
When PCells are placed using a SDL methodology, a layout is automatically generated that reflects the parameter values and connectivity specified by the circuit designer in the schematic. Because the circuit designer does not have to enter any additional information or assign connectivity an enormous amount of time is saved - time that normally would have been spent manually laying out the design. Time savings also comes from the PCell "remembering" how it was connected in the schematic, thereby helping the designer with both automatic and manual routing.
Next big leap
There is little denying the benefits brought to bear by SDL and PCells, but the layout automation they enable comes at a price. Designers using conventional SDL flows are often forced to trade off the time and effort required to set up and use PCells, against a desire to speed layout results. Controllable automation offers a viable means of scaling SDL flows for next-generation custom chips. Using it, designers gain the ability to control not only how often and how much automation is applied, but the overall process as well. Moreover, it is simple and intuitive to implement, enabling layout results that rival even the best manual layout without sacrificing design style or quality.
At the heart of this productivity leap is advanced device generation technology that provides a more flexible and dynamic way of generating an optimized device layout. Because it eliminates the need for time-consuming PCell scripting for the most common PCells, faster layouts can be realised with less effort.
With device generation technology, parameterised devices are used in place of PCells. The devices retain the benefits associated with PCells, but they are independent of the foundry, process or technology being used. They are categorised according to type (e.g., resistors, capacitors, transistors, guard rings, and contacts/vias) and are readable as layout data in GDSII by EDA tools.
A key benefit of using device generation technology is that it enables a more automated and fully controllable SDL flow. The control comes from intuitive, user-friendly device planning, wiring and manipulation capabilities like symbolic device optimisation and device matching. With symbolic device optimisation, designers are free to optimise the device floorplan at a symbolic level without having to worry about parameters, design rules or connectivity (Figure 2). Following completion of the floorplan and design optimisation, a device layout is automatically generated that matches the floorplan. The layout retains the connectivity and sizing defined in the schematic.
This same technology can be applied to resistor and capacitor layout. It can also be used to accelerate more complex layout problems like matching devices. Using a controllable SDL flow, critical layout planning issues can be addressed at a symbolic level and design-rule correct layout automatically generated.
A pattern duplication capability adds even more automation to the SDL flow, enabling efficient layout of repeated circuitry patterns. Repeated patterns can also be optimised to create a more compact layout using a technique called pattern reuse.
To deal with growing circuit size and design complexity, the layout process has been forced to become much more automated, increasing productivity with every technological advance. SDL and PCells represent a significant step forward in design productivity, but next-generation custom chips will undoubtedly demand a further evolution - namely, to controllable automation and advanced device generation technology. The implementation of such advancements is key to scaling today's SDL flow and creating superior layouts with less effort, in less time, and without sacrificing layout density or design style.
SpringSoft | www.springsoft.com
Rich Morse is Technical Marketing and EDA Alliances Manager for Laker Custom IC Design Solutions, SpringSoft
