In stark contrast, analogue design is difficult and slow, and as complexity increases, is fast becoming a serious bottleneck in the IC design flow.  Analogue and mixed signal design tools exist, of course, providing various degrees of increased productivity, but this design process is far harder to automate.  Some say that it is the nature of the beast, that it can never be tamed in the same way. 

The sheer diversity of possibilities in analogue design has led to a multiplicity of tools from specialist and mainstream vendors.  Taking advantage of these tools requires tool interoperability, and this has always been a major issue, especially in the mixed signal domain.  To complicate matters further, analogue and mixed signal design requires detailed knowledge of the target fabrication process. 

Enter Process Design Kits (PDKs)

Over the years, a number of misconceptions have built up concerning what they contain, and what they do not; who produces them; how much they cost and what support is needed.  Essentially, a PDK is a set of data files used to model transistors for a specific process technology at a specific foundry.  Typically, the PDK includes a schematic symbol library, parameterized layout cells (P-cells), Spice models, and technology files related to the design automation flow. 

A library of parameterised layout cells, used to automate device generation, are an integral part of the PDK.  P-cells are not to be confused with standard cells.  P-cells are the very basic transistor-level building blocks of analogue and mixed signal design that embody the process-specific design rules. They reduce the number of DRC iterations in the design verification process and increase the likelihood of a right-first-time design.  P-cells can also be tailored to suit the LVS (layout vs schematic), ERC (electrical rule checking) and DFM (design for manufacture) features of specific EDA tools.

PDKs do not include standard cell libraries, though some PDKs are sometimes integrated with, or delivered with, standard cell libraries.  Generally available (free of charge) from some foundries and sold by third party vendors, standard cell libraries contain transistor-based low-level logic functions such as ‘and’ and ‘or’ gates, flip flops, latches and buffers.  

PDKs should not be confused with the Reference Flow or Reference Tool Flow (RTF) either.  RTFs are foundry-suggested combinations of design tools that have been proven on a particular process, and may be optimised for speed, area, low power or other parameters.  Foundries may highlight specific tools, even specific releases of tools, that have been proven to be interoperable, and which generate the required result on the target process.  Alternatively, RTFs may illustrate a more generic recommendation of the sequence and types of tools that can be used.  Increasingly, RTFs are becoming available with reference designs, demonstrating how detailed, and sometimes complex, circuitry has been created and verified using a particular tool flow. 

Bundled confusion

Most EDA vendors offer support for both PDKs and RTFs, and they may be bundled together.  Some tool vendors may integrate these both with their schematic design suites for example, or with a physical verification technology flow.  Such instances of bundling PDKs with RTFs and other technology files and even the tools themselves, have led to confusion over what precisely is included in a PDK.

Essentially PDKs are no more than an interface between EDA tools and the semiconductor manufacturing process, describing the electrical, yield and performance aspects of the process.  Importantly, PDKs are not only process specific, but also tool flow specific.  Generally, they can only be developed as a collaborative effort between foundry and EDA vendor.  It is essential that a design manager ensures that the PDK (from a foundry) supports the tools he will be using, or the PDK (from an EDA vendor) supports the specific process from the target foundry.

There are clear advantages of working with EDA tools that support the PDKs for the target foundry process.  The primary benefit is to reduce overall design time.  The design set-up time can be significantly reduced, but principally, PDKs save considerable time and effort at the back-end by ensuring from the start that designs are consistent with specific process rules.  PDKs that support advanced routing tools, for example, and interactive automation techniques, such as rule-driven design, can boost productivity tremendously.  Globally, PDKs contribute to improved design quality, greater design consistency and ultimately, higher yields.

However, the investment made by foundries and EDA vendors in PDKs is not insignificant.  For a foundry with many process options (CMOS, BiCMOS, low or high voltage, low or high power, and each on a different geometry) and with customers using tools from different vendors, the effort involved can be huge.  Similarly, for EDA vendors to support or develop a PDK for every process used by every customer can be a daunting task. 

Clearly, when it comes to standardisation, the PDK is a prime candidate. In fact, it has been the target of standards efforts for more than six years, though with little progress until recently. But change is afoot and from now on the PDK development and support process is about to become a whole lot easier. 

Interoperability inspires innovation

TSMC, the largest independent foundry, has thrown its weight behind the two-year-old IPL (Interoperable P-Cell Library) initiative, and has announced interoperable PDKs for its 65nm processes for analogue and mixed signal design.  In principle, TSMC only has to develop one iPDK per process, which is then easily adopted by the many EDA vendors supporting the IPL initiative. 

PDK Checklist: A PDK may include all or a subset of the above

TSMC’s iPDK is said to support a full custom design flow from schematic entry to final layout verification, including technical files for layout creation, pre-layout simulation, layout verification (DRC, LVS, ERC) and post layout simulation.

Other foundries are soon expected to adopt the iPDK concept, and more EDA vendors are likely to join the IPL initiative.  iPDKs are based on the OpenAccess common database from Si2 and open source P-cell development tools.  The critical factor is that for the first time, P-cell libraries developed for a specific process can be used by IC designers using tools from multiple vendors.

The additional benefits that iPDKs bring to the designer are manifold.  Open P-cell libraries mean that full design re-use will be greatly facilitated.  The ability to mix and match ‘best of breed’ tools from different vendors will be much easier.  As a result, it will open up competition among EDA vendors, spurring innovative development of new analogue and mixed signal design automation tools, in the knowledge that they can be more easily, and therefore more likely to be, integrated in the tool flow.  New tools could be adopted more swiftly, helping the designer adopt advanced, more automated methodologies and at higher levels of design integration. This will be particularly important as foundries push geometries down from 65nm to 40nm and beyond.

PDK support packages

Until such time as iPDKs become the norm, analogue and mixed signal IC designers can continue to gain the advantages of standard PDKs.  However, it is always important to check that the chosen EDA vendor provides PDK support for the target process. See the checklist in Figure 1 for a typical PDK support package. Although Cadence is the dominant tool supplier in this sector, and all foundries are likely to provide PDKs matched to Cadence tools, there have always been alternatives.  Some offer lower cost, less complex tool suites and specialist software tools for MEMS design, or advanced design verification, for example. 

From a foundry perspective, major players like TSMC are moving into the analogue and mixed signal arena, but more characteristic of this sector, are smaller, specialist foundries, particularly in Europe.  They also provide PDKs and in addition, look to support customers using tools from other suppliers as well as Cadence.  Fabs are finding that often, a significant proportion of their analogue and mixed signal business is coming from users of tool suites other than, or not solely, Cadence.  

Indeed, since supporting Tanner PDKs directly, more than a third of all submissions to Europe-based X-Fab for example, are from Tanner EDA customers. 

Tanner tools are also supported directly by foundries such as MHS, and L-Foundry, and recently Tanner signed a collaborative development agreement with Tower Jazz for formal PDK development.

Furthermore Tanner provide PDK support for foundries such as AMS, TSMC, UMC and SMIC, amongst others, via organisations such as Europractice and Mosis.

Tanner does not have PDK support for every process at every foundry, of course.  But developing a new PDK need not take months, perhaps only a matter of days or weeks.  Some PDKs may be relatively straightforward to create, especially as Tanner is well used to collaborating with most foundries.  Much depends on the complexity of the customer’s design, the nature of the target process, whether extra library elements are included and optimisation options. 

Tanner’s PDK service is offered free of charge to customers under maintenance, and this typically includes the provision of  schematic libraries, Spice models, layer and GDSII definitions, P-Cells, verification set-ups and parasitic extraction decks.  When used with the Tanner EDA IC design tool suite, the PDKs provide customers with a design flow from schematic generators through schematic-driven layout to full DRC and LVS verification, that is tightly matched to the target process.

With the shift to iPDKs, support for different foundry processes will be much faster and simpler to provide.  Interoperable P-cells will mean that customers can truly benefit from design re-use, and innovative new tools, delivering a timely boost in design productivity as yet higher silicon integration puts pressure on designers.  Looking forward, Tanner will certainly be moving in the direction of iPDKs and OpenAccess.

What does PDK support really mean?

•      Basic schematic symbols (MOS, R, C)
•      Spice models (direct from fab as for H-Spice)
•      Layer setups (name, colour, GDSII, parasitics)
•      T-Cells (as for schematic)
•      Standard DRC rule deck
•      Standard EXT definition deck
•      HiPer PX extraction deck
•      Direct foundry support, or indirect via organisation such as Europractice or MOSIS

What does PDK support not mean?
•      No pads, logic cells, analog or any other complicated/time consuming IPs
•      Days/weeks not months of effort required to produce a new pdk

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