Enhanced early static checks of Finite State Machines and Xilinx IP-based designs

Aldec, Inc., an industry leader in electronic design verification, has expanded the rule-checking capabilities of its popular ALINT-PRO tool in response to increasing verification challenges for complex, large-scale FPGA and ASIC designs. These enhanced capabilities include twice as many FSM checks and new graphical representations to aid state exploration.

“Most issues designers face when implementing FSM-based control blocks tend to be caught during RTL-signoff, using coverage-enabled simulation and/or formal property checking methods,” observes Sergei Zaychenko, Aldec software product manager. “Aldec ALINT-PRO can discover many complex FSM issues long before test stimuli are available. With the latest version of ALINT-PRO users can do FSM-level verifications that will save them a significant amount of verification time further on down the line.”

Another major benefit to users through the 2018.07 release of ALINT-PRO is enhanced setup automation for complex Xilinx Vivado and ISE projects. The extension enables a “push button” flow for early static verification of IP-intensive Xilinx FPGA-targeted designs. A workspace is automatically organised to deliver hierarchical and incremental DRC and CDC analysis, allowing the designer to concentrate on checking custom RTL blocks, while preserving accuracy at the boundaries of IP blocks. Unless an IP block is re-configured in the original design environment it is only being analysed once, and the extracted block-level timing constraints are automatically promoted to enable higher level verification of the main design.

ALINT-PRO 2018.07 Highlights

• Enhanced graphical representations to facilitate the better exploration of the extracted FSMs and reveal FSM-based design issues
• 25 new FSM design rules covering advanced aspects and typical errors
• More than 40 new rules to improve VHDL and Verilog/SystemVerilog RTL coding quality
• Greatly simplified initial setup for Xilinx Vivado/ISE complex IP-based designs
• Hierarchical and Incremental analysis for Out-of-Context (OoC) style Vivado IP blocks
• Support of physically and logically exclusive clock groups
• Introduced basics of multi-mode CDC analysis in simultaneous and case-based modes
• Multi-variant design rule checking settings via Project Configurations 

www.aldec.com/Products/ALINT-PRO